Webpage: Dr. Lynn Fuller
    email:   Lynn.Fuller@rit.edu

Lecture Notes on CMOS Design and Processes

RIT is supporting two different CMOS process technologies.  The older p-well CMOS and SMFL-CMOS has been phased out.  The SUB-CMOS process is used for standard 3.3 Volt Digital and Analog integrated circuits.  This is the technology of choice for teaching circuit design and fabricating CMOS circuits at RIT.  The ADV-CMOS process is intended to introduce our students to process technology that is close to industry state-of-the-art.  The ADV-CMOS process is used to build test structures and develop new technologies at RIT.

RIT p-well CMOS   Lambda = 4 µm Lmin = 8 µm (no longer supported)
RIT SMFL-CMOS  Lambda = 1 µm Lmin = 2 µm (being phased out)
RIT Subµ-CMOS  Lambda = 0.5 µm Lmin = 1.0 µm
RIT Advanced-CMOS Lambda = 0.25 µm Lmin = 0.5 µm

Topic	Power Point Document	Video Link	Video Download
SUB-CMOS Chip Desigers Manual	CmosDesign.pdf	Lecture11	Lecture11.wmv
SUB-CMOS Process Details	SUB-CMOS2009.pdf	Lecture05 Lecture06	Lecture05.wmv Lecture06.wmv
SUB-CMOS Process and Device Calculations	handcalcSUB_CMOS.pdf
Test Results for John Galt Testchip	CMOSTEST.pdf	CMOSTEST Test Manual Test Results	CMOSTEST.wmv
SPICE Parameters for RIT CMOS Processes	SPICE.pdf	SPICE Parameters	SPICE Parameters
SPICE Examples	SPICE Examples.pdf
RIT MOSFET SPICE Models Comparison of Measured and Simulated	MODELS.txt MOSFET_DC_Models.pdf
Introduction to Mentor Graphics Tools	Mentor Tools.pdf
CMOS VLSI Design	CMOS_VLSI_2007.pdf	CMOS VLSI	CMOS_VLSI