CMPE 315: Principles of VLSI Design |
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CMPE 315: Principles of VLSI Design
Section 01 Fall 2018 Instructor: Chintan Patel Office: ITE 322 Office Hours: Mon & Wed, 11:00 AM - 12:00 PM or by appointment Teaching Assistant: Hasib-Al- Rashid Undergraduate Teaching Assistant: Benjamin Thompson Grader: Rachit Sood Office Hours: TBD Meeting Time and Location: Mon & Wed, FA 014, 1:00 - 2:15 PM Lab Discussion: Fri, ITE 375, 1:00 - 2:50 PM Lab: Fri, ITE 375 (you can use ITE 240 also), 3:00 - 4:00 PM Announcements
Check regularly for important class information
Aug 28: Syllabus posted. Course Material
Syllabus: Fall 2018 syllabus Lecture 1: Introduction Lecture 2: CMOS Basics I Lecture 3: CMOS Basics II Lecture 4: IC Technology Lecture 5: Circuit and System Representation Lecture 6: Quality Metrics I Lecture 7: Quality Metrics II Lecture 8: MOS Details Lecture 9: MOS Capacitance and Resistance Model Lecture 10: Inverter DC & AC Response Lecture 11: CMOS Fabrication I Lecture 12: CMOS Fabrication II
End of Midterm Exam Material Lecture 13: Circuit Characterization and Performance Estimation Lecture 14: Logical Effort Lecture 15: Power Dissipation Lecture 16: Interconnect and Wire Engineering Lecture 17: Design Margin, Reliability and Scaling Lecture 18: Combinational Logic Design Lecture 19: Combination Logic Design II Lecture 20: Sequential Logic Design End of Course Material
Lab Submission
Lab Assignment 2 (Extended: Due Mon Sep 24th): Schematics and Spectre Simulations Lab Assignment 3 (Due Mon Oct 1st): Layout, Extraction and Simulations Lab Assignment 4 (Due Fri Oct 12th): D Flip-flop layout and simulations Lab Assignment 5 (Due Wed Oct 24th): Import VHDL, layout and LVS Project
Example test benches and correct outputs
Instructions for running cadence tools
DRC rules for AMI 0.6um technology (Available at MOSIS site) Cadence Incisive (VHDL) Tutorial Cadence IC6 Tutorials
Cadence IC5 Tutorials (OLD TOOLS, USE IC6 TUTORIALS)
VHDL Help
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