This note introduces the
student to the design of digital logic circuits, both combinational and
sequential, and the design of digital systems in a hierarchical, top-down
manner. Topics covered includes : HDLs in the Design Process, VHDL
Entities, Architectures, and Processes, VHDL Names, Signals, and Attributes,
VHDL Operators, VHDL Constructs, VHDL Hierarchical Modeling, VHDL Modeling
Guidelines, Parameterized RAM Modeling, Test Benches, VHDL FSM Modeling, VHDL
Sequential Logic Modeling and Verilog.
This note introduces the
student to the design of digital logic circuits, both combinational and
sequential, and the design of digital systems in a hierarchical, top-down
manner. Topics covered includes : HDLs in the Design Process, VHDL
Entities, Architectures, and Processes, VHDL Names, Signals, and Attributes,
VHDL Operators, VHDL Constructs, VHDL Hierarchical Modeling, VHDL Modeling
Guidelines, Parameterized RAM Modeling, Test Benches, VHDL FSM Modeling, VHDL
Sequential Logic Modeling and Verilog.
This tutorial covers the following topics: Levels of representation and
abstraction, Basic Structure of a VHDL file, Lexical Elements of VHDL, Data
Objects: Signals, Variables and Constants, Data types, Operators, Behavioral
Modeling: Sequential Statements, Dataflow Modeling – Concurrent Statements and
Structural Modeling.