This note introduces the
student to the design of digital logic circuits, both combinational and
sequential, and the design of digital systems in a hierarchical, top-down
manner. Topics covered includes : HDLs in the Design Process, VHDL
Entities, Architectures, and Processes, VHDL Names, Signals, and Attributes,
VHDL Operators, VHDL Constructs, VHDL Hierarchical Modeling, VHDL Modeling
Guidelines, Parameterized RAM Modeling, Test Benches, VHDL FSM Modeling, VHDL
Sequential Logic Modeling and Verilog.
This note covers the
following topics: Brief history of Verilog HDL, Features of Verilog HDL, HDL –
Hardware Description Language, Programming Language V.S. Verilog Verilog HDL HDL,
Time Wheel in Event-Driven Simulation, Different Levels of Abstraction, Top Down
ASIC Design Flow, Escaped Identifiers, Nets and Registers, Operators Used in
Verilog, Syntax of Verilog, Delay and Time Scales, Compiler Directives, User
Defined Primitives, Logic Strength Modeling .
This note introduces the
student to the design of digital logic circuits, both combinational and
sequential, and the design of digital systems in a hierarchical, top-down
manner. Topics covered includes : HDLs in the Design Process, VHDL
Entities, Architectures, and Processes, VHDL Names, Signals, and Attributes,
VHDL Operators, VHDL Constructs, VHDL Hierarchical Modeling, VHDL Modeling
Guidelines, Parameterized RAM Modeling, Test Benches, VHDL FSM Modeling, VHDL
Sequential Logic Modeling and Verilog.