This
note covers the following topics: Graph Theory, Chips, Linear Gate
Arrays, Two-Dimensional Gate Matrix, Transistor Row Placement, Cell Placement,
Routing, Evaluation of BONNCELL Features.
This
note covers the following topics: Graph Theory, Chips, Linear Gate
Arrays, Two-Dimensional Gate Matrix, Transistor Row Placement, Cell Placement,
Routing, Evaluation of BONNCELL Features.