This note
covers the following topics: Chip Design Styles, High Level Synthesis, Register
Allocation in High Level Synthesis, VLSI Circuit Issues, Multilevel
Partitioning, Algorithmic Techniques in VLSI CAD, Sequence-pair based floor
planning technique, Quadratic Placement, Classical placement algorithms ,
Simultaneous level partitioning based PDP, General and Channel Routing, Maze and
Line Routing, Global Routing.
This note introduces full custom
integrated circuit design. Topics covered includes: CMOS processes, mask layout
methods and design, rules, MOS transistor modeling, circuit characterization and
performance estimation, design of combinational and sequential circuits and
logic families, interconnects, several subsystems including adder.
This note covers the following topics:
The Integrated Circuit, Architectural Design, N-channel Depletion Mode
Transistor (De-MOSFET), IC Production Processes, Oxidation, Masking And
Lithography, Etching, Doping, Metallization, MOS And CMOS Fabrication Process,
BICMOS Circuits.
Author(s): Gayatri
Vidhya Parishad, College of Engineering
This note explains the following topics: Sequential Machines, Memory,
Dynamic latch, Design Flow, System Design, Floorplanning, Architecture Design,
Chip Design.
This note explains the following topics: Verilog coding, Metal
Oxide Seminconductor Field Effect Transistor (MOSFET), Fabrication Process and
Layout Design Rules, Propagation Delays in MOS, Power Disipation in CMOS
Circuits, Semiconductor Memories.
This note covers the following topics:Nano-Scale
VLSI Design Challenges, CMOS Logic, VLSI Subsystem Design,Semiconductor
Memories, Source of Variations, Impact of Variations, Device Degradation,
Architecture of Current SOC Chips, Challenges of 3D Implementations and
Low-Power VLSI.
This note explains the basic analog
integrated circuit and system design including design space exploration,
performance enhancement strategies, operational amplifiers, references,
integrated filters, and data converters.
This note
covers the following topics: Chip Design Styles, High Level Synthesis, Register
Allocation in High Level Synthesis, VLSI Circuit Issues, Multilevel
Partitioning, Algorithmic Techniques in VLSI CAD, Sequence-pair based floor
planning technique, Quadratic Placement, Classical placement algorithms ,
Simultaneous level partitioning based PDP, General and Channel Routing, Maze and
Line Routing, Global Routing.